{"id":91862,"date":"2023-11-01T16:44:50","date_gmt":"2023-11-01T07:44:50","guid":{"rendered":"https:\/\/rebellions.ai\/atomus-a-5nm-32-tflops-128-tops-ml-system-on-chip-for-latency-critical-applications\/"},"modified":"2025-08-24T11:21:51","modified_gmt":"2025-08-24T02:21:51","slug":"atomus-a-5nm-32-tflops-128-tops-ml-system-on-chip-for-latency-critical-applications","status":"publish","type":"post","link":"https:\/\/dev-rbln-kr.locomotion.co.kr\/?p=91862","title":{"rendered":"[ISSCC] ATOMUS: A 5nm 32 TFLOPS\/128 TOPS ML System-on-Chip for Latency Critical Applications"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\"><\/p>\n\n<ul class=\"wp-block-list\">\n<li>Rebellions paper has been accepted at ISSCC 2024.<\/li>\n<\/ul>\n\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" src=\"https:\/\/rebellions.ai\/wp-content\/uploads\/2023\/11\/ISSCC-3-1-1024x597.jpg\" alt=\"\" class=\"wp-image-90524\"\/><\/figure>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":5,"featured_media":93057,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[163],"tags":[],"class_list":["post-91862","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-publications"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v25.9 - 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