{"id":92693,"date":"2025-05-02T13:03:00","date_gmt":"2025-05-02T04:03:00","guid":{"rendered":"https:\/\/kr-dev.rebellions.ai\/?p=92693"},"modified":"2025-09-16T10:38:19","modified_gmt":"2025-09-16T01:38:19","slug":"peta-scale-soc-for-massive-ai-serving-rebel-quad","status":"publish","type":"post","link":"https:\/\/dev-rbln-kr.locomotion.co.kr\/?p=92693","title":{"rendered":"Peta-Scale SoC for Massive AI Serving: REBEL-Quad"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">REBEL-Quad is an advanced AI SoC built on a UCIe-Advanced chiplet architecture, designed to meet the extreme compute and memory demands of serving frontier LLMs at massive scale for hyperscalers, AI data centers, and enterprises.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img decoding=\"async\" width=\"440\" height=\"373\" src=\"https:\/\/kr-dev.rebellions.ai\/wp-content\/uploads\/2025\/05\/rebel-quad_1.png\" alt=\"\" class=\"wp-image-92959\" srcset=\"https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/rebel-quad_1.png 440w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/rebel-quad_1-300x254.png 300w\" sizes=\"(max-width: 440px) 100vw, 440px\" \/><figcaption class=\"wp-element-caption\">[Peta-Scale SoC for Massive AI Serving: REBEL-Quad]<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">It features a unified hardware-software stack that maximizes utilization and delivers exceptional performance-per-watt across both compute-bound prefill and memory-bound decoding phases. The chiplet-based design enables hyper scalability without compromising latency or coherence.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img decoding=\"async\" width=\"1144\" height=\"916\" src=\"http:\/\/kr-dev.rebellions.ai\/wp-content\/uploads\/2025\/05\/REBEL-Q_chiplet.png\" alt=\"\" class=\"wp-image-93064\" style=\"width:726px;height:auto\" srcset=\"https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/REBEL-Q_chiplet.png 1144w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/REBEL-Q_chiplet-300x240.png 300w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/REBEL-Q_chiplet-1024x820.png 1024w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/REBEL-Q_chiplet-768x615.png 768w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/REBEL-Q_chiplet-640x512.png 640w\" sizes=\"(max-width: 1144px) 100vw, 1144px\" \/><figcaption class=\"wp-element-caption\">[Figure 1. Block diagram of REBEL-Quad with four homogeneous chiplets]<\/figcaption><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading has-large-font-size\"><strong>Solving Challenges of LLM<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">REBEL-Quad introduces architectural solutions designed for energy-efficient AI inference at massive scale.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<h3 class=\"wp-block-heading has-medium-font-size\"><strong>Unified Mixed Precision Compute Engine<\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Combines FP8\/FP16\/FP32 arithmetic in a single core, boosting compute density by 2.8\u00d7.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<h3 class=\"wp-block-heading has-medium-font-size\"><strong>Predictive DMA &amp; On-Chip Mesh<\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">2.7 \u202fTB\/s effective bandwidth with software-tuned DMA, backed by a 3.3\u00d7 faster mesh fabric.<\/p>\n<\/div>\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\">REBEL-Quad\u2019s exceptional performance-per-watt, starts from its proprietary IP cores. A high-bandwidth on-chip mesh interconnect ensures seamless communication across all cores.<\/p>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-8f761849 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<h3 class=\"wp-block-heading has-medium-font-size\"><strong>Holistic Synchronization<\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Hardware-accelerated peer-to-peer and hierarchical communication enabling seamless distributed execution.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<h3 class=\"wp-block-heading has-medium-font-size\"><strong>Custom Die-to-Die Protocol<\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">1 TB\/s per channel with 11ns inter-chiplet latency, while preserving modularity and enabling various chiplet expansions.<\/p>\n<\/div>\n<\/div>\n\n\n\n<p class=\"has-medium-font-size wp-block-paragraph\">The software stack is tightly coupled to the underlying hardware to enable frictionless scalability to serve frontier models. Backed by a custom die-to-die protocol, REBEL-Quad reliably supports the massive inference demands for hyperscalers and AI data centers.<\/p>\n\n\n\n<h2 class=\"wp-block-heading has-large-font-size\"><strong>Unified Mixed Precision Compute \u2028with Chiplet-Scale Scalability<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Traditional NPUs rely on separate arithmetic blocks for different precision formats (e.g., FP8, FP16, BF16), leading to inefficiencies in both area and dataflow scheduling. REBEL-Quad introduces a unified arithmetic engine supporting per-operand configurable precision, eliminating the need for separate functional units.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">This design enables:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>2.8\u00d7 higher compute density compared to legacy implementations<\/strong><\/li>\n\n\n\n<li><strong>Reduced instruction dependency via hardware-managed wide-issue execution<\/strong><\/li>\n<\/ul>\n\n\n\n<div style=\"height:40px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large is-resized\"><img decoding=\"async\" width=\"1024\" height=\"951\" src=\"https:\/\/kr-dev.rebellions.ai\/wp-content\/uploads\/2025\/05\/mixed-precision-arithmetic-core-1024x951.png\" alt=\"\" class=\"wp-image-92858\" style=\"object-fit:cover;width:756px;height:auto\" srcset=\"https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/mixed-precision-arithmetic-core-1024x951.png 1024w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/mixed-precision-arithmetic-core-300x279.png 300w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/mixed-precision-arithmetic-core-768x713.png 768w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/mixed-precision-arithmetic-core-640x594.png 640w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/mixed-precision-arithmetic-core.png 1036w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">[Figure 2. Unified multi-\/mixed-precision arithmetic core]<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\">The wide-issue mechanism balances memory bandwidth across tensor and vector cores, ensuring simultaneous access to registers and scratchpad memory. These improvements are particularly beneficial in compute-heavy stages of LLM inference, where sustained FP8 throughput is essential. REBEL-Quad achieves 2 PFLOPS (FP8) compute within a single-node four-chiplet package, significantly enhancing performance-per-watt.<\/p>\n\n\n\n<h2 class=\"wp-block-heading has-large-font-size\"><strong>Predictive DMA and High-Bandwidth Memory Access<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">In the decoding phase, token-by-token generation is limited by KV cache memory bandwidth, which scales poorly with longer context windows. To mitigate this, REBEL-Quad implements a predictive, software-configurable DMA engine capable of:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>2.7 TB\/s effective memory bandwidth<\/strong><\/li>\n\n\n\n<li><strong>Simultaneous local and remote HBM access<\/strong><\/li>\n\n\n\n<li><strong>Multi-path routing for bandwidth interleaving<\/strong><\/li>\n<\/ul>\n\n\n\n<div style=\"height:40px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">This DMA is tightly integrated with REBEL-Quad\u2019s custom on-chip mesh interconnect, providing 3.3\u00d7 higher per-core bandwidth over previous architectures. The DMA engine also supports per-task QoS, minimizing latency spikes and dependency stalls across long-tail workloads.<\/p>\n\n\n\n<h2 class=\"wp-block-heading has-large-font-size\"><strong>Hierarchical Synchronization and Peer Communication<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">To sustain performance across distributed workloads, especially in models with complex attention patterns and long-range dependencies, REBEL-Quad employs a full-chip synchronization and communication mechanism.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Key mechanisms include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>A dedicated virtual channel for control signals across the mesh network<\/strong><\/li>\n\n\n\n<li><strong>A centralized synchronization manager that orchestrates execution flow<\/strong><\/li>\n\n\n\n<li><strong>Hardware-accelerated peer-to-peer communication between cores, DMAs, and synchronization units<\/strong><\/li>\n<\/ul>\n\n\n\n<div style=\"height:40px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">The hierarchical communication protocol supports both fine-grained intra-chiplet coordination and scalable inter-chiplet dependency resolution, ensuring maximum utilization across all neural cores during concurrent prefill and decoding. This architecture avoids traditional synchronization bottlenecks and minimizes software overhead, enabling compute-dense execution, high utilization rate, and consequently, maximum performance-per-watt.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img decoding=\"async\" width=\"1024\" height=\"468\" src=\"https:\/\/kr-dev.rebellions.ai\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines-1024x468.png\" alt=\"\" class=\"wp-image-92857\" srcset=\"https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines-1024x468.png 1024w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines-300x137.png 300w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines-768x351.png 768w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines-1536x702.png 1536w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines-640x293.png 640w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/neural-cores-and-DMA-engines.png 1584w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">[Figure 3. Full-chip data transfer utilizing neural cores and DMA engines]<\/figcaption><\/figure>\n<\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img decoding=\"async\" width=\"1024\" height=\"804\" src=\"https:\/\/kr-dev.rebellions.ai\/wp-content\/uploads\/2025\/05\/peer-to-peer-synchronizationsync-manager-1024x804.png\" alt=\"\" class=\"wp-image-92860\" srcset=\"https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/peer-to-peer-synchronizationsync-manager-1024x804.png 1024w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/peer-to-peer-synchronizationsync-manager-300x236.png 300w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/peer-to-peer-synchronizationsync-manager-768x603.png 768w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/peer-to-peer-synchronizationsync-manager-640x503.png 640w, https:\/\/dev-rbln-kr.locomotion.co.kr\/wp-content\/uploads\/2025\/05\/peer-to-peer-synchronizationsync-manager.png 1304w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">[Figure 4. Full-chip peer-to-peer and hierarchical synchronization scheme using the per-chiplet centralized sync manager]<\/figcaption><\/figure>\n<\/div>\n\n\n<h2 class=\"wp-block-heading has-large-font-size\"><strong>Scalable Die-to-Die Protocol for Modular Expansion<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">REBEL-Quad\u2019s modular design is enabled by a custom die-to-die protocol based on UCIe-Advanced, offering:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>1 TB\/s bi-directional per-channel throughput and 11ns full-path inter-chiplet latency<\/strong><\/li>\n\n\n\n<li><strong>Load-store memory semantics across dies<\/strong><\/li>\n\n\n\n<li><strong>Future-proofed via flexible scale-up and scale-out<\/strong><\/li>\n<\/ul>\n\n\n\n<div style=\"height:40px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">This interconnect transforms the multi-chip system into a virtually monolithic unit, while preserving modular scalability for future system expansion. Each chiplet communicates via three UCIe channels, with topology-aware die rotation ensuring horizontal mesh continuity. The protocol is paired with a robust switch network and real-time debug mechanisms to support high-reliability, error-free operation, essential for supporting massive AI serving demands of frontier models, especially for hyperscalers, AI data centers, and enterprises. Future extensibility is planned through I\/O and memory expander chiplets, enabling even broader system configurations with minimal redesign.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">REBEL-Quad delivers the performance, efficiency, and scalability needed to serve next-generation LLMs\u2014without compromise. Its chiplet-based design enables modular upgrades and long-term adaptability, making it an ideal foundation for enterprise-scale AI systems.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>REBEL-Quad is an advanced AI SoC built on a UCIe-Advanced chiplet architecture, designed to meet the extreme compute and memory&#8230;<\/p>\n","protected":false},"author":8,"featured_media":92723,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[145],"tags":[],"class_list":["post-92693","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-white-papers"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v25.9 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Peta-Scale SoC for Massive AI Serving: REBEL-Quad - Rebellions<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/dev-rbln-kr.locomotion.co.kr\/?p=92693\" \/>\n<meta property=\"og:locale\" content=\"ko_KR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Peta-Scale SoC for Massive AI Serving: REBEL-Quad - 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